[컴퓨터구조] Immediate Operands, Load Immediate Value

그냥 add instruction과 addi instruction은 다르다.

addi에서 뒤에 붙은 i는 immediate을 의미한다.

-> constant data included in an instruction

addi x22, x23, 4

여기서 x23은 one register file operand, 4는 one constant value다.

 

주의해야할 점은 subi instruction은 없다는 것이다.

instead, just use a negative integer value.

 

x23에서 1을 빼서 x22에 저장하고 싶어! 라고 하면

subi x22, x23, 1 같지만, subi instruction은 없으므로 우리는

addi x22, x23, -1로 작성할 수 있다.

이유: By reducing the number of instructions supported by CPU, we can simplify hardware design

단순화 측면에서 subi는 unnecessary instruction이기 때문이다.

 

x = x + 1 이라는 단순한 식은

addi x2, x0(zero), 1

add x1, x1, x2

라는 두 줄의 식으로 표현될 수 있다.

(We can make value x2 as 1 before executing operation, it takes multiple steps to perform this simple operation.)

 

그렇다면 위에 나타난 첫 번째 과정에서 zero는 무엇일까?

<The constant zero>

RISC-V register 0 (x0, or 'zero') is the constant(fixed) 0

cannot be overwritten

 

useful for common operations

ex) move (copy) between registers

add x1, x2, zero

라고 한다면 x2에 zero를 더해 x1에 저장하는 것이므로

moving the value of x2 to x1 하는 것이나 다름 없다. (copy의 기능)

 

ex) loading a constant (immediate) value to a register

add x1, x0, 10

라고 한다면 10을 x1에 load 한다는 의미가 된다.

 

여기서 추가로 알아두어야 할 점은

addi x0, x10, x11라고도 쓸 수는 있다는 것이다.

'는'에 볼드를 적용한 건 이유가 있다.

우리는 x0을 이용하여 destination register를 작성할 수 있지만

still valid instruction and can execute, but

result of this operation doesn't change anything from register file.

 

<Load Immediate Value- li instruction>

(memory -> register)

li xd, immediate_value (32 bit)

여기서 xd: destination

 

not a real instruction (pseudo-instruction)

: not supported by CPU itself -> assembly program

ex)

li x1, 100

li x2, 0x10

add x3, x1, x2

 

<Multiply>

ex) 11(2) x 11(2) = 110(2) + 11(2) = 1001(2)

32-bit x 32-bit -> result can be up to 64-bit

need 2 destination registers to completely hold the result

 

"M" Extension for Multiply / Division

The base "RV32I" RISC-V ISA does not contain multiply / division instructions

"RV32IM" version supports multiply / division instructions

 

mul x3, x1, x2

: multiple x1 and x2, and put the lower 32 bits to x3

lower part -> single version to calculate

 

mulh x3, x1, x2

multiply x1 and x2, and put the upper 32 bits to x3

 

But in many cases, we might not need to use all of these 64 bits -> 그냥 lower part만 사용

Although out integer value can be expressed in 32bits, in many cases we might not use all 32 bits.

 

- mulh의 3 versions

mulh x3, x1, x2 (x1, x2 contains signed numbers)

mulhu x3, x1, x2 (x1, x2 contains unsigned numbers)

mulhsu x3, x1, x2 (x1: signed, x2: unsigned)

 

2's complement signed integers

given an n-bit number

-> range: -2^n-1 to +2^n-1 - 1

use the same adder logic with the unsigned integer values

 

programmers distinguish them by using different instructions instead of different type

ex) add x1, x2, x3

만약 float 였다면

fadd x1, x2, x3

let the CPU know that these two registers have floating point values

 

<Division>

div x3, x1, x2     (x1 / x2)

rem x3, x1, x2    (x1 % x2)

divu / remu (unsigned versions)